1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a current sensing read circuit.
2. Description of the Prior Art
Conventional semiconductor memory devices, particularly nonvolatile semiconductor memory devices, can roughly be classified into those with current sensing circuit and those with voltage sensing circuit. Of these the current sensing circuits is of the type which senses the on-current of the memory cell when the cell is energized. Referring to FIG. 6 which illustrates a semiconductor memory device employing a current sensing circuit, this semiconductor device includes a memory cell array 102, a column selector 103 which selects a bit line connected to a memory cell of the memory cell array 102; and a current to voltage converter circuit 280. This circuit 280 comprises an n-channel MOS transistor 203 serving as a transfer transistor with its source connected to the desired bit line selected by the column selector 103, an n-channel MOS transistor 202 serving as a load transistor which is inserted between the drain of the n-channel MOS transistor 203 and a power supply potential, and a dummy feedback circuit 270. The circuit 270 consists of a series connection of an n-channel MOS transistor 204 which receives a precharging signal SAE to its gate, and a circuit formed by a parallel connection of an n-channel MOS transistor 206 which also receives the signal SAE to its gate and an n-channel MOS transistor 205 which has its gate connected to bit line DLi of the memory cell, where the respective drains and the sources of the transistors 206 and 205 are connected in common, and the series connection point FBi serving as the output terminal of the circuit 270 is connected to the gate of the n-channel MOS transistor 203. Moreover, the memory device further comprises a reference array 106, a current to voltage converter circuit 281 for reference which is connected to a bit line DLR connected to a reference memory cell of a reference memory cell array via a switching transistor, and a voltage comparison type differential amplifier circuit 201 which compares output voltage VDi of the current to voltage converter circuit 280 with output voltage VREF of the current to voltage converter circuit 281. Here, the current to voltage converter circuit 281 for reference has the identical configuration with that of the current to voltage converter circuit 280.
The sense amplification operation of data read by the current sensing amplifier will be easy to understand when it is time sequentially classified into precharging period and sensing period. In the precharging stage in the first half, it is general to supply charges to the bit lines DLi and DLR to raise the potentials of these lines to predetermined levels lower than the power supply voltage.
After the bit line potentials are settled as a result of precharging, memory cells MC are selected to generate on-currents in the memory cells MC. The resulting changes in the bit line currents are transmitted to the feedback parts 270 and 271, the transfer transistors 203 and 213 that are controlled by these feedback parts, and the load transistors 202 and 212 for the transfer transistors to generate voltages corresponding to the selected desired memory cell currents.
The roles of the feedback parts 270 and 271 in this process are different in the precharging period in the first half and in the sensing period in the latter half, and the difference becomes conspicuous when an increase in the operating speed is attempted.
In short, in the precharging period in the first half, the speed by which the required charging of the parasitic capacitances of the bit lines DLi and DLR is achieved is an important issue.
In order to attain quick supply of charges by controlling the feedback circuits 270 and 271 in the precharging period, it is necessary to generate feedback signals FBi and FBR that can instantaneously supply large quantities of charges.
Since, however, the potentials of the bit lines DLi and DLR that are clamped by the feedback circuits 270 and 271 are at sufficiently lower levels than that of the power supply voltage, overprecharging is liable to occur if the charge supply capability is set too high.
Once an overprecharging takes place during read operation, there is no route for discharging the charges that are overprecharged to bring them down sufficiently close to the desired levels, so that the reading rate of data will have to be reduced contrary to the intention. In addition, the amplitudes of the voltages input to the feedback circuits 270 and 271 during the precharging are relatively large among all voltages involved in the read operation.
In contrast, during the sensing period in the latter half, it is desirable for stable sensing operation that the feedback outputs do not undergo too large variations with respect to the variations generated in the inputs (that is, the bit line potentials) of the feedback circuits 270 and 271 caused by the memory cells.
Fundamentally, larger amplification factors by the feedback circuits 270 and 271 will lead to raise the amplification factors of the current to voltage converter circuits 280 and 281. However, if one relies too much on the amplification factors of the feedback circuits 270 and 271, then the adverse effect during sensing of the feedback circuit operations acting as noise sources will become noticeable.
Under these circumstances, the feedback signals FBi and FBR for charge supply at precharging are required to show somewhat higher charge supply capability in the first half of the precharging period, while the charge supply capability needs be appropriately restrained in the latter half of the precharging period so as to be able to avoid overprecharging.
In contrast to this, during sensing, it is desirable to output the feedback signals so as not to be affected too much by the potential changes in the bit line.
In this case, the characteristics of the feedback parts 270 and 271 are set to satisfy the situation of an intermediate point between enhancement of the amplification factor and of suppression of overprecharging.
In order to optimize the series of operations to satisfy the intermediate situation mentioned above, it is desirable to set the characteristics of the feedback circuits 270 and 271 so as to vary optimally in the respective stages.
As another example of the conventional semiconductor memory device there may be mentioned the device disclosed in Japanese Patent Applications Laid Open No. Hei 3-207096.
In the semiconductor memory device described above, in the first half of the precharging period, it is necessary to generate feedback signals which are capable of supplying large quantities of charges instantaneously in order to perform control of charges necessary for charging the parasitic capacitances of the bit lines by means of the feedback circuits.
In this case, if the charge supply capability of the feedback circuits is set too high, the potentials of the bit lines are liable to be overprecharged. If overprecharging takes place once, there arises a problem that the rate of read is deteriorated in the reading operation since there is no route for discharging the charges to bring them down to the desired levels.
In contrast, during the sensing period in the latter half, it is desirable that the feedback outputs do not change too much relative to the changes in the bit line potentials generated by the memory cells. Moreover, if the amplification factors of the current to voltage converter circuits are raised too much by means of the feedback circuits, there arises a problem that the operations of the feedback circuits act as noise sources in the sensing operation.